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products and specifications discussed herein ar e subject to change by micron without notice. 256mb: (x72, sr) 244-pin ddr2 mini-rdimm features pdf: 09005aef818e3e75/source: 09005aef818e3df5 micron technology, inc., reserves the right to change products or specifications without notice. htf5c32x72k.fm - rev. b 2/07 en 1 ?2005 micron technology, inc. all rights reserved. ddr2 sdram mini-rdimm mt5htf3272(p)k ? 256mb for component data sheets, refer to micron?s web site: www.micron.com features ? 244-pin, mini-registered dual in-line memory module (mini-rdimm) ? fast data transfer rates: pc-3200, pc2-4200, or pc2-5300 ? supports ecc error detection and correction ? 256mb (32 meg x 72) ?v dd = v dd q = +1.8v ?v ddspd = +1.7v to +3.6v ? jedec-standard 1.8v i/ o (sstl_18-compatible) ? differential data strobe (dqs, dqs#) option ?4 n -bit prefetch architecture ? single rank ? multiple internal device banks for concurrent operation ? supports duplicate output strobe (rdqs/rdqs#) ? programmable cas# latency (cl) ? posted cas# additive latency (al) ? write latency = read latency - 1 t ck ? programmable burst lengths: 4 or 8 ? adjustable data-output drive strength ? 64ms, 8,192-cycle refresh ? on-die termination (odt) ? serial presence-det ect (spd) with eeprom ? gold edge contacts figure 1: 244-pin mini-rdimm (mo-244 r/c b) notes: 1. contact micron for industrial temperature module offerings. 2. cl = cas (read) latency; registered mode will add one clock cycle to cl. options marking ?parity p ? operating temperature 1 ? commercial (0c t a + 70c) none ? industrial (?40c t a + 85c) i ?package ? 244-pin mini-rdimm (pb-free) y ? frequency/cas latency 2 ? 3.0ns @ cl = 5 (ddr2-667) -667 ? 3.75ns @ cl = 4 (ddr2-533) -53e ? 5.0ns @ cl = 3 (ddr2-400) -40e ?pcb height ? 30mm (1.18in) mo d ule hei g ht: 30.0mm (1.18in) table 1: key timing parameters speed grade industry nomenclature data rate (mt/s) t rcd (ns) t rp (ns) t rc (ns) cl = 5 cl = 4 cl = 3 -667 pc2-5300 667 533 400 15 15 55 -53e pc2-4200 ? 533 400 15 15 55 -40e pc2-3200 ? 400 400 15 15 55
pdf: 09005aef818e3e75/source: 09005aef818e3df5 micron technology, inc., reserves the right to change products or specifications without notice. htf5c32x72k.fm - rev. b 2/07 en 2 ?2005 micron technology, inc. all rights reserved. 256mb: (x72, sr) 244-pin ddr2 mini-rdimm features notes: 1. data sheets for the base device s can be found on micron?s web site. 2. all part numbers end with a two-place code (not shown), designating component and pcb revisions. consult factory for current revision codes. example: mt5htf3272ky-40ed1 . table 2: addressing 256mb refresh count 8k row addressing 8k (a0?a12) device bank addressing 4 (ba0, ba1) device page size per bank 1kb device configuration 512mb (32 meg x 16) column addressing 1k (a0?a9) module rank addressing 1 (s0#) table 3: part numbers and timing parameters ? 256mb base device: mt47h32m16 1 , 512mb ddr2 sdram part number 2 module density configuration module bandwidth memory clock/ data rate latency (cl- t rcd- t rp) mt5htf3272(p)ky-667__ 256mb 32 meg x 72 5.3 gb/s 3.0ns/667 mt/s 5-5-5 mt5htf3272(p)ky-53e__ 256mb 32 meg x 72 4.3 gb/s 3.75ns/533 mt/s 4-4-4 mt5htf3272(p)ky-40e__ 256mb 32 meg x 72 3.2 gb/s 5.0ns/400 mt/s 3-3-3
pdf: 09005aef818e3e75/source: 09005aef818e3df5 micron technology, inc., reserves the right to change products or specifications without notice. htf5c32x72k.fm - rev. b 2/07 en 3 ?2005 micron technology, inc. all rights reserved. 256mb: (x72, sr) 244-pin ddr2 mini-rdimm pin assignments and descriptions pin assignments and descriptions notes: 1. pin 56 is nc for non-parity and e rr _o ut and parity. 2. pin 68 is nc fo r non-parity and p ar _i n for parity. table 4: pin assignments 244-pin mini-rdimm front 244-pin mini-rdimm back pin symbol pin symbol pin symbol pin symbol pin symbol pin symbol pin symbol pin symbol 1v ref 32 v ss 63 v dd q94dqs5# 123 v ss 154 dq28 185 a3 216 nc 2v ss 33 dq24 64 a2 95 dqs5 124 dq4 155 dq29 186 a1 217 v ss 3 dq0 34 dq25 65 v dd 96 v ss 125 dq5 156 v ss 187 v dd 218 dq46 4dq135v ss 66 v ss 97 dq42 126 v ss 157 dm3 188 ck0 219 dq47 5v ss 36 dqs3# 67 v ss 98 dq43 127 dm0 158 nc 189 ck0# 220 v ss 6 dqs0# 37 dqs3 68 2 nc/ p ar _i n 99 v ss 128 nc 159 v ss 190 v dd 221 dq52 7dqs038 v ss 69 v dd 100 dq48 129 v ss 160 dq30 191 a0 222 dq53 8v ss 39 dq26 70 a10 101 dq49 130 dq6 161 dq31 192 ba1 223 v ss 9 dq2 40 dq27 71 ba0 102 v ss 131 dq7 162 v ss 193 v dd 224 rfu 10 dq3 41 v ss 72 v dd 103 sa2 132 v ss 163 cb4 194ras#225 rfu 11 v ss 42 cb0 73 we# 104 nc 133 dq12 164 cb5 195 v dd q226 v ss 12 dq8 43 cb1 74 v dd q105 v ss 134 dq13 165 v ss 196 s0# 227 dm6 13 dq9 44 v ss 75 cas# 106 dqs6# 135 v ss 166 dm8 197 v dd q228 nc 14 v ss 45 dqs8# 76 v dd q 107 dqs6 136 dm1 167 nc 198 odt0 229 v ss 15 dqs1# 46 dqs8 77 nc 108 v ss 137 nc 168 v ss 199 nc 230 dq54 16 dqs1 47 v ss 78 nc 109 dq50 138 v ss 169 cb6 200 v dd 231 dq55 17 v ss 48 cb2 79 v dd q 110 dq51 139 rfu 170 cb7 201 nc 232 v ss 18 reset# 49 cb3 80 nc 111 v ss 140 rfu 171 v ss 202 v ss 233 dq60 19 nc 50 v ss 81 v ss 112 dq56 141 v ss 172 nc 203 dq36 234 dq61 20 v ss 51 nc 82 dq32 113 dq57 142 dq14 173 v dd q 204 dq37 235 v ss 21 dq10 52 v dd q83dq33114 v ss 143 dq15 174 nc 205 v ss 236 dm7 22 dq11 53 cke0 84 v ss 115 dqs7# 144 v ss 175 v dd 206 dm4 237 nc 23 v ss 54 v dd 85 dqs4# 116 dqs7 145 dq20 176 nc 207 nc 238 v ss 24 dq16 55 nc 86 dqs4 117 v ss 146 dq21 177 nc 208 v ss 239 dq62 25 dq17 56 1 nc/ e rr _o ut 87 v ss 118 dq58 147 v ss 178 v dd q 209 dq38 240 dq63 26 v ss 57 v dd q 88 dq34 119 dq59 148 dm2 179 a12 210 dq39 241 v ss 27 dqs2# 58 a11 89 dq35 120 v ss 149 nc 180 a9 211 v ss 242 sda 28 dqs2 59 a7 90 v ss 121 sa0 150 v ss 181 v dd 212 dq44 243 scl 29 v ss 60 v dd 91 dq40 122 sa1 151 dq22 182 a8 213 dq45 244 v ddspd 30 dq18 61 a5 92 dq41 152 dq23 183 a6 214 v ss 31 dq19 62 a4 93 v ss 153 v ss 184 v dd q215 dm5
pdf: 09005aef818e3e75/source: 09005aef818e3df5 micron technology, inc., reserves the right to change products or specifications without notice. htf5c32x72k.fm - rev. b 2/07 en 4 ?2005 micron technology, inc. all rights reserved. 256mb: (x72, sr) 244-pin ddr2 mini-rdimm pin assignments and descriptions table 5: pin descriptions symbol type description odt0 input (sstl_18) on-die termination: odt (registered high) enables termi nation resistance internal to the ddr2 sdram. when enabled, odt is only applied to each of the following pins: dq, dqs, dqs#, rdqs, rdqs#, cb, and dm. the odt input will be ignored if disabled via the load mode (lm) command. ck0, ck0# input (sstl_18) clock: ck and ck# are differential clock inputs . all address and control input signals are sampled on the crossing of the positive edge of ck and negative edge of ck#. output data (dqs and dqs/dqs#) is referenced to the crossings of ck and ck#. cke0 input (sstl_18) clock enable: cke (registered high) activates an d cke (registered low) deactivates clocking circuitry on the ddr2 sdram. s0# input (sstl_18) chip select: s# enables (registered low) and di sables (registered high) the command decoder. all commands are masked when s# is registered high. s# provides for external rank selection on systems with multiple ranks. s# is considered part of the command code. ras#, cas#, we# input (sstl_18) command inputs: ras#, cas#, and we# (along with s#) define the command being entered. ba0, ba1 input (sstl_18) bank address inputs: ba0?ba1 define to which device bank an active, read, write, or precharge command is being applied. ba0?ba1 define which mode register, including mr, emr, emr(2), or emr(3), is loaded during the lm command. a0?a12 input (sstl_18) address inputs: provide the row address for active commands and the column address and auto precharge bit (a10) for read/write co mmands to select one location out of the memory array in the respective bank. a10 sampled during a precharge command determines whether the precharge applies to one device bank (a10 low, device bank selected by ba0?ba1) or all device banks (a 10 high). the address inputs also provide the op-code during an lm command. p ar _i n input (sstl_18) parity bit for the ad dress and control bus. scl input (sstl_18) serial clock for presence-detect: scl is used to synchronize the presence-detect data transfer to and from the module. sa0?sa2 input (sstl_18) presence-detect address inputs: these pins are used to configure the presence-detect device. reset# input (sstl_18) asynchronously forces all regi stered outputs low when reset# is low. this signal can be used during power-up to ensure that cke is low and dqs are high-z. dq0?dq63 i/o (sstl_18) data input/output: bidirectional data bus. dqs0?dqs8, dqs0#?dqs8# i/o (sstl_18) data strobe: output with read data, input with write data for source synchronous operation. edge-aligned with re ad data, center-aligned with wr ite data. dqs# is only used when differential data strobe mode is enab led via the lm command. dqs9#?dqs17# are only used when rdqs# is enabled via the lm command. dm0?dm8 i/o (sstl_18) input data mask: dm is an input mask si gnal for write data. inpu t data is masked when dm is sampled high along with that input data during a write access. dm is sampled on both edges of dqs. although dm pins are inpu t-only, the dm loading is designed to match that of dq and dqs pins. if rd qs is enabled, dqs9#?dqs17# are used only during the read command. cb0?cb7 i/o (sstl_18) check bits. sda i/o (sstl_18) serial presence-detect data: sda is a bidirectional pin used to transfer addresses and data into and out of the presen ce-detect portion of the module. e rr _o ut output (open drain) parity error foun d on the address and control bus. v dd /v dd q supply power supply: 1.8v 0.1v. v ref supply sstl_18 reference voltage.
pdf: 09005aef818e3e75/source: 09005aef818e3df5 micron technology, inc., reserves the right to change products or specifications without notice. htf5c32x72k.fm - rev. b 2/07 en 5 ?2005 micron technology, inc. all rights reserved. 256mb: (x72, sr) 244-pin ddr2 mini-rdimm pin assignments and descriptions v ss supply ground. v ddspd supply serial eeprom positive power supply: +1.7v to +3.6v. nc ? no connect : these pins should be left unconnected. rfu ? reserved for future use. table 5: pin descriptions (continued) symbol type description
pdf: 09005aef818e3e75/source: 09005aef818e3df5 micron technology, inc., reserves the right to change products or specifications without notice. htf5c32x72k.fm - rev. b 2/07 en 6 ?2005 micron technology, inc. all rights reserved. 256mb: (x72, sr) 244-pin ddr2 mini-rdimm functional block diagram functional block diagram figure 2: functional block diagram a0 s pd eeprom a1 a2 s a0 s a1 s a2 s da sc l wp r e g i s t e r pll u5 p ar _i n s 0# ba0?ba1/ba2 a0?a12 ra s # c a s # we# c ke0 odt0 re s et# e rr _o ut r s 0#: ddr2 s dram rba0 ? rba1/rba2: ddr2 s dram ra0 ? ra12: ddr2 s dram rra s #: ddr2 s dram r c a s #: ddr2 s dram rwe#: ddr2 s dram r c ke0: ddr2 s dram rodt0: ddr2 s dram c k0 c k0# ddr2 s dram ddr2 s dram ddr2 s dram ddr2 s dram ddr2 s dram re g ister re s et# u 6 u4 v ref v ss ddr2 s dram ddr2 s dram v dd / v dd q v dd s pd s pd eeprom ddr2 s dram dq0 dq1 dq2 dq3 dq4 dq5 dq 6 dq7 dq dq dq dq dq dq dq dq dq32 dq33 dq34 dq35 dq3 6 dq37 dq38 dq39 r s 0# dq s 0 dq s 0# dm0 dq s 4 dq s 4# dm4 dq s 1 dq s 1# dm1 dq s 5 dq s 5# dm5 dq s 2 dq s 2# dm2 dq s6 dq s6 # dm 6 dq s 3 dq s 3# dm3 dq s 7 dq s 7# dm7 dq s 8 dq s 8# dm8 dq dq dq dq dq dq dq dq dq8 dq9 dq10 dq11 dq12 dq13 dq14 dq15 dq dq dq dq dq dq dq dq dq40 dq41 dq42 dq43 dq44 dq45 dq4 6 dq47 dq dq dq dq dq dq dq dq dq1 6 dq17 dq18 dq19 dq20 dq21 dq22 dq23 dq dq dq dq dq dq dq dq dq48 dq49 dq50 dq51 dq52 dq53 dq54 dq55 dq dq dq dq dq dq dq dq dq24 dq25 dq2 6 dq27 dq28 dq29 dq30 dq31 dq dq dq dq dq dq dq dq dq5 6 dq57 dq58 dq59 dq 6 0 dq 6 1 dq 6 2 dq 6 3 dq dq dq dq dq dq dq dq c b0 c b1 c b2 c b3 c b4 c b5 c b 6 c b7 dq dq dq dq dq dq dq dq dq dq dq dq dq dq dq dq cs # cs # cs # cs # cs # ldq s ldq s # ldm udq s udq s # udm ldq s ldq s # ldm ldq s ldq s # ldm ldq s ldq s # ldm ldq s ldq s # ldm udq s udq s # udm udq s udq s # udm udq s udq s # udm udq s udq s # udm v dd u1 u2 u7 u8 u3 v ss
pdf: 09005aef818e3e75/source: 09005aef818e3df5 micron technology, inc., reserves the right to change products or specifications without notice. htf5c32x72k.fm - rev. b 2/07 en 7 ?2005 micron technology, inc. all rights reserved. 256mb: (x72, sr) 244-pin ddr2 mini-rdimm general description general description the mt5htf3272(p)k ddr2 sdram module is a high-speed, cmos, dynamic random- access 256mb memory module organized in a x72 configuration. this ddr2 sdram module uses an internally configured 4-bank (512mb) ddr2 sdram device. ddr2 sdram modules use double data rate architecture to achieve high-speed opera- tion. the double data rate architecture is es sentially a 4n-prefetch architecture with an interface designed to transfer two data words per clock cycle at the i/o pins. a single read or write access for the ddr2 sdram module effectively consists of a single 4n-bit- wide, one-clock-cycle data transfer at the internal dram core and four corresponding n-bit-wide, one-half-clock-cycle data transfers at the i/o pins. a bidirectional data strobe (dqs, dqs#) is transmitted externally, along with data, for use in data capture at the receiver. dqs is a strobe transmitted by the ddr2 sdram device during reads and by the memory controller during writes. dqs is edge- aligned with data for reads and center-aligned with data for writes. ddr2 sdram modules operate fr om a differential clock (ck and ck#); the crossing of ck going high and ck# going low will be referred to as the positive edge of ck. commands are registered at every positive edge of ck. input data is registered on both edges of dqs, and output data is referenced to both edges of dqs, as well as to both edges of ck. register and pll operation ddr2 sdram modules operate in registered mode, where the command/address input signals are latched in the registers on the ri sing clock edge and sent to the ddr2 sdram devices on the following rising clock edge (data access is delayed by one clock cycle). a phase-lock loop (pll) on the module receives and redrives the differential clock signals (ck, ck#) to the ddr2 sdram devices. the register(s) and pll reduce address, command, control, and clock signal loading by isolating dram from the system controller. pll clock timing is defined by jedec specifications and ensured by use of the jedec clock reference board. registered mode will add one clock cycle to cl. serial presence-detect operation ddr2 sdram modules incorporate serial presence-detect (spd). the spd function is implemented using a 2,048-bi t eeprom. this nonvolatile storage device contains 256 bytes. the first 128 bytes can be programmed by micron to identify the module type and various sdram organizations and timing parameters. the remaining 128 bytes of storage are available for use by the customer. system read/write operations between the master (system logic) and the slave eeprom device occur via a standard i 2 c bus using the dimm?s scl (clock) and sda (data) signals, together with sa (2:0), which provide eight unique dimm/eeprom addresse s. write protect (wp) is tied to v ss on the module, permanently disabling hardware write protect.
pdf: 09005aef818e3e75/source: 09005aef818e3df5 micron technology, inc., reserves the right to change products or specifications without notice. htf5c32x72k.fm - rev. b 2/07 en 8 ?2005 micron technology, inc. all rights reserved. 256mb: (x72, sr) 244-pin ddr2 mini-rdimm electrical specifications electrical specifications stresses greater than those listed in ta ble 6 may cause perman ent damage to the module. this is a stress rating only, and func tional operation of the module at these or any other conditions above those indicated in each device?s data sheet is not implied. exposure to absolute maximum rating condit ions for extended periods may affect reli- ability. notes: 1. the refresh rate is requ ired to double when 85c < t c 95c. 2. for further information, refer to technical no te tn-00-08: ?thermal applications,? available on micron?s web site. input capacitance micron encourages designers to simulate the performance of the module to achieve optimum values. simulations are significantly more accurate and realistic than a gross estimation of module capacitance when inductance and delay parameters associated with trace lengths are used in simulations. jedec modules are currently designed using simulations to close timing budgets. component ac timing an d operating conditions recommended ac operating conditions are given in the ddr2 component data sheets. component specifications are available on micron?s web site. module speed grades correlate with component speed grades, as shown in table 7. table 6: absolute maximum ratings symbol parameter min max units v dd /v dd q v dd /v dd q supply voltage relative to v ss ?0.5 +2.3 v v in , v out voltage on any pin relative to v ss ?0.5 +2.3 v i i input leakage current ; any input 0v v in v dd ; v ref input 0v v in 0.95v; (all other pins not under test = 0v) command/address ras#, cas#, we#, s#, cke, dm, odt, ba ?5 +5 a ck, ck# ?250 +250 i oz output leakage current; 0v v out v dd q; dqs and odt are disabled dq, dqs, dqs# ?5 +5 a i vref v ref leakage current; v ref = valid v ref level ?10 +10 a t a module ambient operating temperature commercial 0+70c industrial ?40 +85 c t c 1 ddr2 sdram component case operating temperature 2 commercial 0+85c industrial ?40 +95 c table 7: module and component speed grades module speed grade component speed grade -667 -3 -53e -37e -40e -5e
pdf: 09005aef818e3e75/source: 09005aef818e3df5 micron technology, inc., reserves the right to change products or specifications without notice. htf5c32x72k.fm - rev. b 2/07 en 9 ?2005 micron technology, inc. all rights reserved. 256mb: (x72, sr) 244-pin ddr2 mini-rdimm electrical specifications i dd specifications ta bl e 8 : dd r2 i dd specifications and conditions ? 256mb values shown for mt47h32m16 ddr2 sdram only an d are computed from values specified in the 512mb (32 meg x 16) component data sheet parameter/condition symbol -667 -53e -40e units operating one bank active-precharge current: t ck = t ck (i dd ), t rc = t rc (i dd ), t ras = t ras min (i dd ); cke is high, s# is high between valid commands; address bus inputs are switch ing; data bus inpu ts are switching i dd 0 600 550 550 ma operating one bank active-read-precharge current: i out = 0ma; bl = 4, cl = cl (i dd ), al = 0; t ck = t ck (i dd ), t rc = t rc (i dd ), t ras = t ras min (i dd ), t rcd = t rcd (i dd ); cke is high, s# is high between valid commands; address bus inputs are switching; da ta pattern is same as i dd 4w i dd 1 750 675 650 ma precharge power-down current: all device banks idle; t ck = t ck (i dd ); cke is low; other control and address bus in puts are stable; data bus inputs are floating i dd 2p 35 35 35 ma precharge quiet standby current: all device banks idle; t ck = t ck (i dd ); cke is high, s# is high; other control and address bus inputs are stable; data bus inputs are floating i dd 2q 275 225 200 ma precharge standby current: all device banks idle; t ck = t ck (i dd ); cke is high, s# is high; other co ntrol and address bus inpu ts are switching; data bus inputs are switching i dd 2n 300 250 225 ma active power-down current: all device banks open; t ck = t ck (i dd ); cke is low; other control and address bus inputs are stable; data bus inputs are floating fast pdn exit mr[12] = 0 i dd 3p 175 150 125 ma slow pdn exit mr[12] = 1 60 60 60 ma active standby current: all device banks open; t ck = t ck (i dd ), t ras = t ras max (i dd ), t rp = t rp (i dd ); cke is high, s# is high between valid commands; other control an d address bus inputs ar e switching; data bus inputs are switching i dd 3n 350 300 250 ma operating burst write current: all device banks open; continuous burst writes; bl = 4, cl = cl (i dd ), al = 0; t ck = t ck (i dd ), t ras = t ras max (i dd ), t rp = t rp (i dd ); cke is high, s# is high betw een valid commands; address bus inputs are switching; data bus inputs are switching i dd 4w 1,250 1,025 800 ma operating burst read current: all device banks open; continuous burst reads; i out = 0ma; bl = 4, cl = cl (i dd ), al = 0; t ck = t ck (i dd ), t ras = t ras max (i dd ), t rp = t rp (i dd ); cke is high, s# is high between valid commands; address bus inputs are switch ing; data bus inpu ts are switching i dd 4r 1,175 975 775 ma burst refresh current: t ck = t ck (i dd ); refresh command at every t rfc (i dd ) interval; cke is high, s# is high betw een valid commands; other control and address bus inputs are switching; data bus inpu ts are switching i dd 5 925 875 850 ma self refresh current: ck and ck# at 0v; cke 0.2v; other control and address bus inputs are floating ; data bus inputs are floating i dd 6353535ma operating bank interleave read current: all device banks interleaving reads; i out = 0ma; bl = 4, cl = cl (i dd ), al = t rcd (i dd ) - 1 x t ck (i dd ); t ck = t ck (i dd ), t rc = t rc (i dd ), t rrd = t rrd (i dd ), t rcd = t rcd (i dd ); cke is high, s# is high between valid command s; address bus inputs are stable during deselects; data bus inputs are switching i dd 7 1,750 1,700 1,700 ma
pdf: 09005aef818e3e75/source: 09005aef818e3df5 micron technology, inc., reserves the right to change products or specifications without notice. htf5c32x72k.fm - rev. b 2/07 en 10 ?2005 micron technology, inc. all rights reserved. 256mb: (x72, sr) 244-pin ddr2 mini-rdimm register and pll specifications register and pll specifications notes: 1. timing and switching specifications for the register listed above are cr itical for proper oper- ation of the ddr2 sdram regist ered dimms. these are meant to be a subset of the param- eters for the specific device us ed on the module. detailed in formation for this register is available in jedec standard jesd82. table 9: register specifications sstu32866 devices or equivalent jesd82-10 parameter symbol pins condition min max units dc high-level input voltage v ih ( dc ) address, control, command sstl_18 v ref ( dc ) + 125 v dd q + 250 mv dc low-level input voltage v il ( dc ) address, control, command sstl_18 0 v ref ( dc ) - 125 mv ac high-level input voltage v ih ( ac ) address, control, command sstl_18 v ref ( dc ) + 250 v dd mv ac low-level input voltage v il ( ac ) address, control, command sstl_18 0 v ref ( dc ) - 250 mv output high voltage v oh parity output lvcmos 1.2 ? v output low voltage v ol parity output lvcmos ? 0.5 v input current i i all pins v i = v dd q or v ss q?5 5a static standby i dd all pins reset# = v ss q (io = 0) ? 100 a static operating i dd all pins reset# = v ss q; v i = v ih ( ac ) or v il ( dc ) io = 0 ?40ma dynamic operating (clock tree) i ddd n/a reset# = v dd , v i = v ih ( ac ) or v il ( ac ), io = 0; ck and ck# switching 50% duty cycle ?varies by manufacturer a dynamic operating (per each input) i ddd n/a reset# = v dd , v i = v ih ( ac ) or v il ( ac ), io = 0; ck and ck# switching 50% duty cycle; one data input switching at t ck/2, 50% duty cycle ?varies by manufacturer a input capacitance (per device, per pin) c i all inputs except reset# v i = v ref 250mv; v dd q = 1.8v 2.5 3.5 pf input capacitance (per device, per pin) c i reset# v i = v dd q or v ss q?varies by manufacturer pf
pdf: 09005aef818e3e75/source: 09005aef818e3df5 micron technology, inc., reserves the right to change products or specifications without notice. htf5c32x72k.fm - rev. b 2/07 en 11 ?2005 micron technology, inc. all rights reserved. 256mb: (x72, sr) 244-pin ddr2 mini-rdimm register and pll specifications notes: 1. pll timing and swit ching specifications are critical for proper operation of the ddr2 dimm. this is a subset of parameters for the specific pll used. detailed pll in formation is available in jedec standard jesd82. table 10: pll specifications cu877 device or equivalent jesd82-8.01 parameter symbol pins condition min max units dc high-level input voltage v ih reset# lvcmos 0.65 v dd ?v dc low-level input voltage v il reset# lvcmos ? 0.35 v dd v input voltage (limits) v in reset#, ck, ck# ?0.3 v dd q + 0.3 v dc high-level input voltage v ih ck, ck# differential input 0.65 v dd ?v dc low-level input voltage v il ck, ck# differential input ? 0.35 v dd v input differential-pair cross voltage v ix ck, ck# differential input (v dd q/2) - 0.15 (v dd q/2) + 0.15 v input differential voltage v id ( dc ) ck, ck# differential input 0.3 v dd q + 0.4 v input differential voltage v id ( ac ) ck, ck# differential input 0.6 v dd q + 0.4 v input current i i reset# v i = v dd q or v ss q?1010a ck, ck# v i = v dd q or v ss q ?250 250 a output disabled current i odl reset# = v ss q; v i = v ih ( ac ) or v il ( dc ) 100 ? a static supply current i ddld ck = ck# = low ? 500 a dynamic supply i dd n/a ck, ck# = 270 mhz, all outputs open (not connected to pcb) ?300ma input capacitance c in each input v i = v dd q or v ss q23pf table 11: pll clock driver timing requirements and switching characteristics parameter symbol min max units stabilization time t l? 15s input clock slew rate t ls i 1.0 4 v/ns ssc modulation frequency 30 33 khz ssc clock input frequency deviation 0.0 ?0.50 % pll loop bandwidth (?3db from unity gain) 2.0 ? mhz
pdf: 09005aef818e3e75/source: 09005aef818e3df5 micron technology, inc., reserves the right to change products or specifications without notice. htf5c32x72k.fm - rev. b 2/07 en 12 ?2005 micron technology, inc. all rights reserved. 256mb: (x72, sr) 244-pin ddr2 mini-rdimm serial presence-detect serial presence-detect notes: 1. to avoid spurious start and stop conditions, a minimum delay is placed between scl = 1 and the falling or rising edge of sda. 2. this parameter is sampled. 3. for a restart condition, or following a write cycle. 4. the spd eeprom write cycle time ( t wrc) is the time from a vali d stop condition of a write sequence to the end of the eeprom intern al erase/program cycl e. during the write cycle, the eeprom bus interface circuit is disabled, sda rema ins high due to pull-up resis- tance, and the eeprom does not respond to its slave address. table 12: serial presence-detec t eeprom dc operating conditions all voltages referenced to v ss ; v ddspd = +1.7v to +3.6v parameter/condition symbol min max units supply voltage v ddspd 1.7 3.6 v input high voltage: logic 1; all inputs v ih v ddspd 0.7 v ddspd + 0.5 v input low voltage: logic 0; all inputs v il ?0.6 v ddspd 0.3 v output low voltage: i out = 3ma v ol ?0.4v input leakage current: v in = gnd to v ddspd i li 0.10 3 a output leakage current: v out = gnd to v ddspd i lo 0.05 3 a standby current i sb 1.6 4 a power supply curren t, read: scl clock frequency = 100 khz i cc r 0.4 1 ma power supply current, write: scl clock frequency = 100 khz i cc w 23ma table 13: serial presence-detec t eeprom ac operating conditions all voltages referenced to v ss ; v ddspd = +1.7v to +3.6v parameter/condition symbol min max units notes scl low to sda data-out valid t aa 0.2 0.9 s 1 time the bus must be free before a new transition can start t buf 1.3 ? s data-out hold time t dh 200 ? ns sda and scl fall time t f?300ns2 data-in hold time t hd:dat 0 ? s start condition hold time t hd:sta 0.6 ? s clock high period t high 0.6 ? s noise suppression time con stant at scl, sda inputs t i?50ns clock low period t low 1.3 ? s sda and scl rise time t r?0.3s2 scl clock frequency f scl ? 400 khz data-in setup time t su:dat 100 ? ns start condition setup time t su:sta 0.6 ? s 3 stop condition setup time t su:sto 0.6 ? s write cycle time t wrc ? 10 ms 4
pdf: 09005aef818e3e75/source: 09005aef818e3df5 micron technology, inc., reserves the right to change products or specifications without notice. htf5c32x72k.fm - rev. b 2/07 en 13 ?2005 micron technology, inc. all rights reserved. 256mb: (x72, sr) 244-pin ddr2 mini-rdimm serial presence-detect table 14: serial presence-detect matrix byte description entry (version) 256mb 0 number of spd bytes used by micron 128 80 1 total number of bytes in spd device 256 08 2 fundamental memory type ddr2 sdram 08 3 number of row addresses on sdram 13 0d 4 number of column addresses on sdram 9, 10 0a 5 dimm height and module ranks 30mm, single rank 60 6 module data width 72 48 7 reserved 000 8 module voltage interface levels sstl 1.8v 05 9 sdram cycle time, t ck (cl = max value, see byte 18) -667 -53e -40e 30 3d 50 10 sdram access from clock, t ac (cl = max value, see byte 18) -667 -53e -40e 45 50 60 11 module configuration type ecc ecc and parity 02 06 12 refresh rate/type 7.81s/self 82 13 sdram device width (primary sdram) 16 10 14 error-checking sdram data width 16 10 15 reserved 000 16 burst lengths supported 4, 8 0c 17 number of banks on sdram device 404 18 cas latencies supported -667 (5, 4, 3) -53e/-40e (4, 3) 38 18 19 module thickness 01 20 ddr2 dimm type mini-rdimm 10 21 sdram module attributes 1 pll; 1 register 04 22 sdram device attributes: weak driver (01) and 50 odt (03) -667 -53e/-40e 03 01 23 sdram cycle time, t ck, max cl - 1 -667 -53e/-40e 3d 50 24 sdram access from ck, t ac, max cl - 1 -667 -53e -40e 45 50 60 25 sdram cycle time, t ck, max cl - 2 -667 -53e/-40e 50 00 26 sdram access from ck, t ac, max cl - 2 -667 -53e/-40e 45 00 27 min row precharge time, t rp 3c 28 min row active-to-row active, t rrd 28 29 min ras#-to-cas# delay, t rcd 32 30 min ras# pulse width, t ras -667/-53e -40e 2d 28 31 module rank density 128mb, 256mb, 512mb 40
pdf: 09005aef818e3e75/source: 09005aef818e3df5 micron technology, inc., reserves the right to change products or specifications without notice. htf5c32x72k.fm - rev. b 2/07 en 14 ?2005 micron technology, inc. all rights reserved. 256mb: (x72, sr) 244-pin ddr2 mini-rdimm serial presence-detect notes: 1. the t rc spd values shown are jede c ddr2 device specification values. the actual micron ddr2 device specification is t rc = 55ns for all speed grades. 32 address and command setup time, t is b -667 -53e -40e 20 25 35 33 address and command hold time, t ih b -667 -53e -40e 27 37 47 34 data/data mask input setup time, t ds b -667/-53e -40e 10 15 35 data/data mask input hold time, t dh b -667 -53e -40e 17 22 27 36 write recovery time, t wr 3c 37 write-to-read command delay, t wtr -667/-53e -40e 1e 28 38 read-to-precharge command delay, t rtp 1e 39 memory analysis probe 00 40 extension for bytes 41 and 42 00 41 min active-to-active/refresh time, t rc 1 -667/-53e -40e 3c 37 42 min auto refresh-to-active/aut o refresh command period, t rfc 69 43 sdram device max cycle time, t ck (max) 80 44 sdram device max dqs?dq skew time, t dqsq -667 -53e -40e 18 1e 23 45 sdram device max read data hold skew factor, t qhs -667 -53e -40e 22 28 2d 46 pll relock time 0f 47?61 optional features , not supported 00 62 spd revision release 1.2 12 63 checksum for bytes 0?62 ecc/ecc and parity -667 -53e -40e 7e/82 29/2d 90/94 64 manufacturer?s jedec id code micron 2c 65?71 manufacturer?s jedec id code (continued) ff 72 manufacturing location 1?12 01?0c 73?90 module part number (ascii) ? variable data 91 pcb identification code 1?9 01?09 92 identification c ode (continued) 000 93 year of manufacture in bcd ? variable data 94 week of manufacture in bcd ? variable data 95?98 module serial number ? variable data 99?127 reserved for manufacturer-specific data 00 128?255 reserved for customer-specific data ff table 14: serial presence-detect matrix (continued) byte description entry (version) 256mb
? 8000 s. federal way, p.o. box 6, boise, id 83707-0006, tel: 208-368-3900 prodmktg@micron.com www.micron.com customer comment line: 800-932-4992 micron, the m logo, and the micron logo ar e trademarks of micron technology, inc. all other trademarks are the property of their respective owners. this data sheet contains minimum and maximum limits specified ov er the complete power supply and temperature range for production devices. althou gh considered final, these specifications are subject to change, as further product development and data characte rization sometimes occur. pdf: 09005aef818e3e75/source: 09005aef818e3df5 micron technology, inc., reserves the right to change products or specifications without notice. htf5c32x72k.fm - rev. b 2/07 en 15 ?2005 micron technology, inc. all rights reserved. 256mb: (x72, sr) 244-pin ddr2 mini-rdimm module dimensions module dimensions figure 3: 244-pin ddr2 mini-rdimm notes: 1. all dimensions are in millimeters (i nches); max/min or typical (typ) where noted. 2. the dimensional diagram is for reference on ly. refer to the jedec mo document for com- plete design dimensions. 82.127 (3.233) 81.873 (3.223) front view 30.152 (1.187) 29.848 (1.175) 20.0 (0.787) typ 10.0 (0.394) typ 1.0 (0.039) typ 2.0 (0.079) r x2 1.0 (0.039) r x2 0.50 (0.02) r 1.80 (0.071) d x2 6.0 (0.236) typ 2.0 (0.079) typ 78.0 (3.071) typ 0.60 (0.024) typ 0.45 (0.018) typ pin 1 pin 122 42.9 (1.689) typ back view 3.3 (0.130) typ 3.6 (0.142) typ 33.6 (1.323) typ 38.4 (1.512) typ 3.2 (0.126) typ 3.80 (0.150) max 1.10 (0.043) 0.90 (0.035) pin 244 pin 123 u1 u2 u3 u4 u6 u7 u8 u5 no dram devices this side of module

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